SpaceWire Router IP core
The SpaceWire Router IP core provides a complete routing and interfacing solution for high data-rate on-board satellite networking. It is fully compliant with the SpaceWire standard ECSS-E-ST-50-12C plus the extensions Protocol Identifier (PID) and Remote Memory Access Protocol (RMAP).
The SpaceWire Router IP cell features a parametrizable number of SpaceWire links and relevant routing switch plus a programmable router table, a dedicated decoder for RMAP, a timecode interface and a status/error interface all accessible by a 32-bit AMBA/AHB bus interface. The router table binds the unique logical address of the destination node in the network with a physical output port of the router. The timecode interface distributes system time thus changing the event-driven SpaceWire network in a time-triggered one. The SpaceWire Router can be timecode master or timecode slave of a SpaceWire network.
- Customisable to fulfil user needs
- 100 Mbps / 8 links in Microsemi RTAX2000 FPGA
- Validated in ESA space project
- Interoperability successfully tested with commercial SpaceWire products
- Time-code Master/Slave
- Programmable router
- via SpW by RMAP or direct access
- via AHB bus
- Fault-tolerant IP with EDAC FIFOs