The JESD204 standard enables interoperability between data converters and logic devices from different manufacturers, allowing ADCs, DACs, FPGAs and ASICs to be selected independently and reused across different applications. As converter performance and channel density increase, system designs are often limited not only by the converters themselves, but also by interconnect complexity, I/O pin count and the need to transfer continuous high-bandwidth data streams efficiently. JESD204 provides a standardized serial interface specifically tailored to these requirements, reducing interface overhead while supporting scalable, lane-based data transfer. IngeniArs JESD204 IP Core implements a technology-independent, fully configurable JESD204-compliant link layer, easing integration in FPGA- and ASIC-based systems built around standard logic resources, PLLs and SERDES macros.
JESD204 IP Core
Keywords: 64B/66B,
64B/80B,
8B/10B,
ADC,
ASIC,
AXI4,
CRC12,
DAC,
FPGA,
high-bandwidth data streams,
JESD204,
JESD204A,
JESD204B,
JESD204C,
Multi-lane,
SERDES,
Subclass 0,
Subclass 1,
Subclass 2,
Technologies ADM Versal VCK190 Microchip PolarFire MPF300 Nano Xplore NG-Ultra,
Technologies AMD Versal VCK190 Microchip PolarFire MPF300; NanoXplore NG-Ultra
Key features
- Coded in technology-independent highly configurable VHDL
- Compliant with JESD204C standard
- Backward compatible with JESD204B and JESD204A standards
- Supports lane rates up to 12.5 Gbps (B) and 32.45 Gbps (C) with configurable number of lanes
- Supports the following encoding options 8B/10B; 64B/66B; 64B/80B
- Supports the following subclass operational modes 0; 1; 2
- Supports enabling/disabling of the scrambler/descrambler
- Supports CRC12 for 64B/66B and 64B/80B
- Standard interfaces for easy integration based on AXI-Stream for data and AXI4-Lite for configuration/status
- Supports error reporting over the AXI4-Lite configuration status interface
- Supports test modes selection and enabling
- Optional mitigation techniques to safely operate in space environment Dead-lock free FSM design with one-hot-coding
- Characterization on the following commercial and space qualified FPGA
- Technologies ADM Versal VCK190 Microchip PolarFire MPF300 Nano Xplore NG-Ultra
Other information
Technologies/Applications
- JESD204
Competencies
- FPGA/ASIC design
- IP Core design
- Verification
Downloads
JESD204 Brochure v1.0