Products

​​CCSDS 131.3-B DVB-S2/S2X Transmitter IP Core​

Keywords: 16-/32-/64-/128-/256-APSK, 8PSK, ASIC, CCSDS 131.3-B, Encoder, ETSI EN 302 307-1, ETSI EN 302 307-2, FPGA, IP Core, LDPC, Microchip PolarFire RT, Modulator, QPSK, Satellite Downlink, Telemetry, Transmitter, Xilinx XQRKU060

A considerable number of Earth Observation missions are based on small satellites class and embark payloads producing substantial data rates, thus requiring a reliable, efficient and economical payload data transmitter specialised for medium to high data rates (i.e., from hundred Mb/s to several Gb/s). Such missions would benefit from employing state-of-the-art coding and modulation standard, allowing to exploit the protection offered by modern coding techniques while at the same time maximizing the supported data rates by using spectral efficient modulation formats. The DVB-S2/S2X Transmitter IP Core is fully compliant with the CCSDS 131.3-B standard and compliant to the ETSI EN 302 307-1/302 307-2 standards. The DVB-S2 transmitter combines Low Density Parity Check (LDPC) codes with modulations ranging from QPSK to 8PSK and 16-APSK, 32-APSK. The DVB-S2X extension increases the flexibility providing new coding rates and new 64APSK128-APSK, and 256-APSK modulation formats. This broad set of coding rates and modulation formats enable fine-grained system configuration, allowing the transmitter to be tailored to a wide range of mission-specific requirements. 

Key features

 
  • Optional Square-Root Raised Cosine (SRRC) baseband filtering
  • Coded in technology-independent highly configurable VHDL
  • Fully compliant with CCSDS 131.3-B standard
  • Compliant with ETSI EN 302 307-1 and EN 302 307-2 standard
  • Standard interfaces for easy integration based on AXI-Stream and AXI4-Lite standards
  • Optional symbol pre-distortion to mitigate non linearity
  • Optional mitigation techniques for safely operate in space environment: EDAC on internal memories - dead-lock free FSM design with one-hot-coding
  • Characterization on the following commercial and space qualified FPGA technologies: AMD XQRKU060; Microchip RTG4; Microchip PolarFire
  • High data-rate IP core option for symbol rates higher than 1200 Mbaud and input data rates higher than 5.3 Gb/s (DVB-S2) and 7.1 Gb/s (DVB-S2X)

Other information

Technologies/Applications

  • CCSDS 131.3-B
  • ETSI EN 302 307-1
  • ETSI EN 302 307-2

Competencies

  • FPGA/ASIC design
  • IP Core design
  • Verification
  • Digital signal processing

Downloads

CCSDS 131.3-B DVBS2/S2X Transmitter IP Core Brochure v1.0

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