CCSDS 131.2-B Encoder/Modulator IP Core

Keywords: 16-/32-/64-/128-/256-APSK, 8PSK, ASIC, BCH, CCSDS 131.2-B, Encoder, FPGA, IP Core, Microsemi RTG4, Modulator, PDT, QPSK, Satellite Downlink, SCCC, Telemetry, Xilinx XQRKU060

A considerable number of Earth Observation missions are based on small satellites class and embark payloads producing substantial data rates, thus requiring a reliable, efficient and economical payload data transmitter specialised for mid-range data rate, i.e. few hundred Mb/s.
Such missions would benefit from employing state-of-the-art coding and modulation standard, allowing to exploit the protection offered by modern coding techniques while at the same time maximizing the supported data rates by using spectral efficient modulation formats.

The CCSDS 131.2-B Encoder/Modulator IP Core is fully compliant with the CCSDS 131.2-B standard, combining powerful Serially Concatenated Convolutional Codes (SCCC) with modulations ranging from QPSK to 8PSK and 16-, 32- and 64-APSK, for a total of 27 Modulation and Coding formats (ModCods).

In addition, the IP Core also supports the extended range of ModCods, involving 128-APSK and 256-APSK modulations with combined SCCC/BCH coding.

Such flexibility, thanks to the number of modulation and coding formats (ModCod) provided, will help configuring the system to better adapt to the specific target requirements.

The CCSDS Telemetry Transmitter IP Core is part of ESA IP Core portfolio.

Key features

  • Fully compliant with CCSDS 131.2-B standard
  • Support of all the 27 ModCods in a single instantiation for high capacity FPGA technologies for space (e.g. Microsemi RTG4 Xilinx Virtex 5QV and Xilinx Kintex Ultrascale XQRKU060)
  • High data-rate IP Core option for symbol rates higher than 500 Mbaud and input data rates higher than 3 Gb/s
  • Low-complexity IP Core option for implementation on antifuse technology (e.g. RTAX2000 FPGA)
  • Includes symbol pre-distortion to mitigate non linearity
  • Optional Square-Root Raised Cosine baseband filtering
  • Optional SEE mitigation mechanisms
  • IP core generator Graphical User Interface to configure and generate the IP core according to the needs of the end-user
  • Validated on the new Microsemi RTG4 development kit
  • Coded in technology-independent and highly configurable VHDL

Other information


  • CCSDS 131.2-B


  • FPGA/ASIC design
  • IP Core design
  • Verification
  • Digital signal processing


CCSDS Telemetry Transmitter IP Core Brochure

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