The IP core implements the forward segment of the Pseudo-Noise (PN) ranging system, designed to support both transmission and reception operations. The transmission section generates the PN ranging signal in compliance with the CCSDS 414.1-B standard, utilizing a local code epoch generator to produce the signal that is to be sent to the satellite. The receiving section locks onto the re-generated echo signal returned by the satellite, measures the two-way round-trip time of the signal, and calculates the distance between the satellite and the round station with high precision. The IP core can be configured to implement either the T4B code or the T23B code. Additionally, the user can select different chip rates, in compliance with the specifications outlined in the standard. Modulation index is a parameter that can be adjusted by the user to properly optimise the transmission, acquisition and tracking phases of the PN ranging signal.
CCSDS 414.1-B PN Ranging Ground System IP Core
Keywords: CCSDS 414.1-B,
FPGA,
Ground Station,
IP Core,
PN ranging,
Satellite communications
Key features
- Coded in technology-independent VHDL
- Compliant with CCSDS 414.1-B standard
- Selectable T2B or T4B PN code
- Selectable modulation index
- Selectable chip rate
- I/O interfaces based on AXI-Stream standard for easy integration
- Configuration interface based on AXI4-Lite standard for easy integration
- Characterization on AMD XQRKU060
Other information
Technologies/Applications
- CCSDS 414.1-B
Competencies
- FPGA/ASIC design
- IP Core design
- Verification
- Digital signal processing