Keywords: ASIC, CSPRNG, Cybersecurity, Entropy source, FPGA, IP Core, RNG, TRNG

The RNG IP Core is a module able to generate random numbers, a primitive function widely used in encryption and cybersecurity applications.

Usually random numbers are employed to generate encryption keys or secret data to be shared between communication entities: the higher the level of entropy of random numbers the higher the level of security they offer.

The RNG IP Core engine is mainly composed by two blocks: a Deterministic Random Bit Generator (DRBG) and an embedded True Random Number Generator (TRNG).

For the architecture implemented, the DRBG mechanism has been chosen from those approved by the NIST and specified in the standard NIST SP 800-90A. The Hash DRBG with SHA2-256 as cryptographic core (i.e., based on the SHA2 algorithm) proved to be the most efficient solution between logical complexity and throughput during random bits generation, offering 256 bits of security strength.

The TRNG design comprehends both the entropy source device and internal health tests logic. Internal health tests perform statistical quality check of the output: they detect significant deviations from the normal average value due to changed environmental conditions (e.g., temperature, humidity, or electric field) as recommended by the standard NIST SP 800-90B.

Key features

  • Simple host interface or AMBA AXI bus interface (on request)
  • High throughput and area efficient IP Core for random bit sequences generation
  • Internal entropy source with embedded health test (upon prototyping on target technology)
  • Built in self-test for failure detection
  • DRBG based on SHA2 algorithm
  • Internal scalable architecture to meet throughput requirements (i.e. multicore SHA support)
  • Implementation results on Xilinx UltraScale+ FPGA technology. Area: 15714 CLBs; Throughput: 0.84 Gbps

Other information



  • FPGA/ASIC design
  • IP Core design
  • Verification

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