SHA Engine

Keywords: ASIC, Cybersecurity, FPGA, Hash function, IP Core, SHA-3, SHA2

The Secure Hash Algorithm (SHA) is a family of cryptographic hash functions developed and distributed by NIST.

Our SHA Engine is composed of 2 independent cores. The first one is a SHA2 core, consisting in several functions (i.e., SHA2-224, SHA2-256, SHA2-384, SHA2-512), to be employed in widely used security applications and protocols, such as TLS and SSL, PGP, SSH, S/MIME, IPsec. The second is a SHA-3 core, which also implements several functions (i.e., SHA-3-224, SHA-3-256, SHA-3-384, SHA-3-512).

SHA-3 is the most recent member of the SHA family as it has been released in 2015, and it employs features of the Keccak cryptographic primitive family.

Both the SHA2/-3 cores of our SHA Engine are accompanied by a hardware padder module, with the purpose of making the total length of the input message an integer multiple of 512 or 1024 bits (for SHA2), or 1152, 1088, 832 or 576 bits (for SHA-3), depending on the original digest size.

The hardware implementation of this operation allows to reduce the amount of operations which the software should perform, significantly reducing the total execution time of drivers and/or software routines.

Key features

  • Simple host interface or AMBA AXI bus interface (on request)
  • High throughput and area efficient IP Core for SHA2 and SHA-3 algorithms
  • Compliant with FIPS 180-2/3/4 and FIPS 202 NIST standards
  • Customizable solution to fulfil user needs
  • Internal padding module available: byte-oriented and/or bit-oriented padding operation (on request)
  • Low power / low complexity / high frequency design
  • Multiple output digest length support: 224/256/384/512

Other information



  • FPGA/ASIC design
  • IP Core design
  • Verification

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