SpaceWire Router IP Core

Keywords: AMBA AXI, ASIC, Configurable ports, Decoder, DMA, ECSS-E-ST-50-12C, Encoder, FPGA, High data-rate, IP Core, On-board satellite communication, On-board satellite network, RMAP, Router, Routing, Serial communication link, SpaceWire

The SpaceWire Router IP Core offers a configurable and flexible solution for high data-rate routing switch functionality for on-board satellite networking.

It is based on the SpaceWire protocol, defining bi-directional, full-duplex, serial data communication link, and it is compliant with the SpaceWire standard ECSS-E-ST-50-12C.

The SpaceWire Router IP Core features a parameterized number of SpaceWire ports, based on the SpaceWire CODEC IP Core, and host-side data ports, based on simple asynchronous FIFO interfaces.

The host data ports can be equipped (on request) with Direct Memory Access (DMA) functionality and standard bus interface such as AMBA AXI.

The SpaceWire Router IP Core has been validated and prototyped in ESA project.

Key features

  • Highly customisable to fulfil user needs
  • Compliant with ECSS-E-ST-50-12C (routing switch specification)
  • Up to 31 SpaceWire and/or host data ports
  • SpaceWire TX data-rate and link start mode programmability for each available SpaceWire port
  • Time-code distribution support
  • SpaceWire links configuration/check and addresses mapping via SpaceWire packets
  • Optional support to RMAP commands (under development)
  • SpaceWire links configuration/check also possible through dedicated host port
  • Synthesized on rad-tolerant FPGA and other devices
  • Path addressing | logical addressing | regional addressing support
  • Host data ports with simple FIFO-based interface or optional DMA / AMBA / AXI bus interface (on request)

Other information


  • SpaceWire


  • FPGA/ASIC design
  • IP Core design
  • Verification


SpaceWire Router IP Core Brochure

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