The DVB-S2/S2X Receiver IP core is a complete solution to implement the core functions of a receiver compliant with the CCSDS 131.3-B standard and partially compliant to those defined in the ETSI 302 307-1 (DVB-S2) standard…

Coming Soon Telemetry Tracking and Command (TT&C) is a satellite sub-system that allows communication between the spacecraft and the ground station. Such systems are based on coding schemes that are defined in…

A considerable number of Earth Observation missions are based on small satellites class and embark payloads producing substantial data rates, thus requiring a…

The IP core implements the forward segment of the Pseudo-Noise (PN) ranging system, designed to support both transmission and reception operations. The transmission section generates the PN ranging signal in compliance with…

The CCSDS 131.2-B Receiver IP Core is a complete solution to implement the core functions of a receiver compliant with the CCSDS 131.2-B standard: this standard has been conceived for Low…

The ESA project “On-Board health monitoring System for SATCOM” aims to develop an innovative Failure Detection, Isolation and Recovery (FDIR) system based on Artificial Intelligence. A specific focus is given to the…

As Microchip Technology Inc. Design Partner, IngeniArs S.r.l. profile page is now available on Microchip website! Click here to visit IngeniArs profile page at Microchip website. Discover which IP cores…

The ECC Accelerator Suite is our IP Core dedicated to accelerate asymmetric-key cryptographic schemes based on Elliptic-Curve Cryptography (ECC) and ECC arithmetic operations. The ECC Accelerator Suite is…

The RNG IP Core is a module able to generate random numbers, a primitive function widely used in encryption and cybersecurity applications. Usually random numbers are employed…

The Secure Hash Algorithm (SHA) is a family of cryptographic hash functions developed and distributed by NIST. Our SHA Engine is composed of 2 independent cores. The…