The ECC Accelerator Suite is our IP Core dedicated to accelerate asymmetric-key cryptographic schemes based on Elliptic-Curve Cryptography…
Verification is the process of demonstrating that the design meets the specified requirements. All IngeniArs products undergo a formal process of verification to ensure that all the requirements are fully met with the total coverage of functionality. Typically, the verification process and the design process are separated in order to avoid biasing from the design process and therefore to have a more effective verification process. A detailed verification plan is produced together with a requirement traceability matrix to ensure that every requirement is covered and to trace possible failures back to the requirements. With respect to FPGA / ASIC / IP Core design, the verification process is typically performed by simulation of the Hardware Description Language (HDL) code. IngeniArs verification methods rely on advanced modern techniques based on SystemVerilog, but also more “traditional” verification methods based on VHDL/Verilog test-benches are performed depending on the design and verification goal.
Verification is a process that is included in all IngeniArs developments, but it is also offered “as a service”. This can be particularly useful for a customer to have a fully independent verification process. The customer provides at least the design and the requirements document and, starting from these, IngeniArs can produce the Verification Plan and Verification Report including requirement/code coverage analysis.
Verification is a process that is included in all IngeniArs developments, but it is also offered “as a service”. This can be particularly useful for a customer to have a fully independent verification process. The customer provides at least the design and the requirements document and, starting from these, IngeniArs can produce the Verification Plan and Verification Report including requirement/code coverage analysis.
The RNG IP Core is a module able to generate random numbers, a primitive function widely used in…
The Secure Hash Algorithm (SHA) is a family of cryptographic hash functions developed and distributed by NIST.
The Crypto-AES IP Core performs hardware acceleration of symmetric-key algorithms based on the Advanced Encryption Standard (AES) cipher,…
The SpaceART® SpaceWire Sniffer unit allows the analysis of SpaceWire communication between two nodes at character level, with no…
SpaceART® is a complete testing solution for high speed links in space applications. SpaceART® supports both SpaceWire (SpW)…
WizardLink is a family of transceivers produced by Texas Instruments and in particular, for space applications, the TI TLK2711…
The SpaceFibre Router IP Core offers a configurable and flexible solution for very high data-rate routing switch functionality for…
SpaceFibre is the ESA standard (ECSS-E-ST-50-11C) for very high speed serial communication links between the units of the satellite.
The SpaceWire Router IP Core offers a configurable and flexible solution for high data-rate routing switch functionality for on-board…
The SpaceWire CODEC IP Core is a very compact IP Core providing a complete and configurable interfacing solution for…
A considerable number of Earth Observation missions are based on small satellites class and embark payloads producing substantial…
“ACM TESTBED” is an European Space Agency project, aimed at implementing a Copernicus reference testbed to accurately model the new…
“High rate flexible high-order SCCC communications system for Science X-band” is an European Space Agency project. It aims at developing…
European space missions both for Earth observation and science (e.g. Euclid, Metop-SG) are more and more demanding very…
“IP Core for medium data rate PDT” is an European Space Agency project for the implementation of a…
Next week our space crew will be at Space Tech Expo USA, taking place on May 2-4 2023 at Long…
You will find us at ESA SESP 2023 next week in ESTEC, The Netherlands. See you there!…
Between the 14th and 16th of March we will be at the 5th edition of SEFUW, the SpacE FPGA Users…
IngeniArs will be golden sponsor of the 4th Italian Space Startup Competition, taking place from 12…
We are approaching to the Space Tech Expo Europe, the fifth edition of Europe’s largest B2B event for the space…
Only a few days left to the International SpaceWire and SpaceFibre Conference – ISC 2022! Though the pandemic situation has…
We are very proud to announce that IngeniArs profile page is now available on SATSEARCH website! Take a moment to visit…
We are very thankful to ITA – Italian Trade Agency and ITA – Italian Trade Agency – Sydney for giving visibility to Italian aerospace…
IngeniArs at the Industry Space Days 2022 (28-29 Sept. 2022) organised and hosted by the ESA at ESTEC facilities, to showcase…
IngeniArs is going to join this year the International Astronautical Congress – IAC 2022, from 18 to…
IngeniArs participated to the 37th Space Symposium edition, on April 4 – 7, 2022 in Colorado…
Take a moment to watch our new corporate video available on our YouTube channel:…
IngeniArs S.r.l. today at Agenzia Spaziale Italiana in Rome for taking part in the bilateral cooperation between Italian and Norwegian…
We are very proud to announce that we are Xilinx Certified Partner now! We would like to thank Xilinx for…
The new University of Pisa Spin-off website is now available online: spinoff.unipi.it IngeniArs profile is…
On 14th April at 10:00 AM CEST we will join the interesting B2B workshop “Italy Japan space cooperation for emerging…
We are so excited to announce that IngeniArs new website is finally online! Discover more about our technologies,…
After 5 years of Professor Luca Fanucci’s great leadership, Giuseppe Gentile becomes the new CEO of the company. We are happy to…