Verification is the process of demonstrating that the design meets the specified requirements. All IngeniArs products undergo a formal process of verification to ensure that all the requirements are fully met with the total coverage of functionality. Typically, the verification process and the design process are separated in order to avoid biasing from the design process and therefore to have a more effective verification process. A detailed verification plan is produced together with a requirement traceability matrix to ensure that every requirement is covered and to trace possible failures back to the requirements. With respect to FPGA / ASIC / IP Core design, the verification process is typically performed by simulation of the Hardware Description Language (HDL) code. IngeniArs verification methods rely on advanced modern techniques based on SystemVerilog, but also more “traditional” verification methods based on VHDL/Verilog test-benches are performed depending on the design and verification goal.
Verification is a process that is included in all IngeniArs developments, but it is also offered “as a service”. This can be particularly useful for a customer to have a fully independent verification process. The customer provides at least the design and the requirements document and, starting from these, IngeniArs can produce the Verification Plan and Verification Report including requirement/code coverage analysis.