IngeniArs is able to manage the entire design and development flow of FPGA and ASIC applications, from the drafting of system specifications to architecture design, from verification to hardware prototyping with implementation and validation of the final system. For each design activity, both internal for its products and external for its customers and/or partners, IngeniArs applies its own quality system and in particular its own design procedure, prepared with the aim of responding as efficiently as possible to the specific needs highlighted by the individual activity. The steps typically followed, with related documentation production, are development planning, drafting/consolidation of technical requirements, feasibility and risk analysis, architectural definition/description, planning and execution of verification and/or validation, prototyping/implementation on hardware platform, preparation of datasheet and/or user manual. In the space field, the design procedure applies guidelines derived from the European Cooperation for Space Standardisation (ECSS) standards, therefore each FPGA and ASIC application development activity follows an approach as near as possible to the principles set out by the ECSS.
ECC Accelerator Suite

ECC Accelerator Suite

The ECC Accelerator Suite is our IP Core dedicated to accelerate asymmetric-key cryptographic schemes based on Elliptic-Curve Cryptography…

RNG IP Core

RNG IP Core

The RNG IP Core is a module able to generate random numbers, a primitive function widely used in…

SHA Engine

SHA Engine

The Secure Hash Algorithm (SHA) is a family of cryptographic hash functions developed and distributed by NIST.

Crypto-AES IP Core

Crypto-AES IP Core

The Crypto-AES IP Core performs hardware acceleration of symmetric-key algorithms based on the Advanced Encryption Standard (AES) cipher,…

SpaceART® SpaceWire Sniffer

SpaceART® SpaceWire Sniffer

The SpaceART® SpaceWire Sniffer unit allows the analysis of SpaceWire communication between two nodes at character level, with no…

SPACEART® – SpaceWire / SpaceFibre Analyser Real Time

SPACEART® – SpaceWire / SpaceFibre Analyser Real Time

SpaceART® is a complete testing solution for high speed links in space applications. SpaceART® supports both SpaceWire (SpW)…

WizardLink TLK equivalent IP Core

WizardLink TLK equivalent IP Core

WizardLink is a family of transceivers produced by Texas Instruments and in particular, for space applications, the TI TLK2711…

SpaceFibre Router IP Core

SpaceFibre Router IP Core

The SpaceFibre Router IP Core offers a configurable and flexible solution for very high data-rate routing switch functionality for…

SpaceFibre CODEC IP Core

SpaceFibre CODEC IP Core

SpaceFibre is the ESA standard (ECSS-E-ST-50-11C) for very high speed serial communication links between the units of the satellite.

SpaceWire Router IP Core

SpaceWire Router IP Core

The SpaceWire Router IP Core offers a configurable and flexible solution for high data-rate routing switch functionality for on-board…

SpaceWire CODEC IP Core

SpaceWire CODEC IP Core

The SpaceWire CODEC IP Core is a very compact IP Core providing a complete and configurable interfacing solution for…

CCSDS 131.2-B Encoder/Modulator IP Core

CCSDS 131.2-B Encoder/Modulator IP Core

A considerable number of Earth Observation missions are based on small satellites class and embark payloads producing substantial…

ACM TESTBED

ACM TESTBED

“ACM TESTBED” is an European Space Agency project, aimed at implementing a Copernicus reference testbed to accurately model the new…

HIGH RATE FLEXIBLE HIGH-ORDER SCCC COMMUNICATIONS SYSTEM FOR SCIENCE X-BAND

HIGH RATE FLEXIBLE HIGH-ORDER SCCC COMMUNICATIONS SYSTEM FOR SCIENCE X-BAND

“High rate flexible high-order SCCC communications system for Science X-band” is an European Space Agency project. It aims at developing…

SIMPLE

SIMPLE

European space missions both for Earth observation and science (e.g. Euclid, Metop-SG) are more and more demanding very…

IP Core for medium data rate PDT

IP Core for medium data rate PDT

“IP Core for medium data rate PDT” is an European Space Agency project for the implementation of a…

MILANOFINANZA SPEAKS ABOUT INGENIARS ON ESA SPACE RIDER

MILANOFINANZA SPEAKS ABOUT INGENIARS ON ESA SPACE RIDER

Milano Finanza speaks about IngeniArs on ESA Space Rider, the automated robotic laboratory which will be launched on Vega-C in…

INGENIARS AT ITALY-JAPAN SPACE COOPERATION WORKSHOP

INGENIARS AT ITALY-JAPAN SPACE COOPERATION WORKSHOP

On 14th April at 10:00 AM CEST we will join the interesting B2B workshop “Italy Japan space cooperation for emerging…

INGENIARS IS ON MICROCHIP WEBSITE

INGENIARS IS ON MICROCHIP WEBSITE

As Microchip Technology Inc. Design Partner, IngeniArs S.r.l. profile page is now available on Microchip website! Click here to…

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